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Digital Integration Features Register Reference Manual
V1.04

Introduction

This manual acts as a reference for the Digital Integration Features available on our various PCI Express Digital I/O products (and related cards!) .

It should be used as an adjunct to the standard product reference manual (.pdf) available on the product webpage or in the software install package.

The Digital Integration Features add advanced capabilities to the input and output bits of these Digital I/O products. Pulse Train Generation (including PWM), Pulse Width Measurement (including PWM/duty-cycle), Edge detection IRQs, and Edge-detection Counter with overflow IRQs are available on all applicable models.

In addition, all of these models provide their I/O registers in both the original "I/O Mapped" and new, faster, "Memory Mapped" modes.

Feature Description

Input Features

Advanced Change-of-State Detection IRQs

  • 8 bits of individually enabled, edge-selectable, change-of-state detection latches and IRQs

Selectable-edge Counting with Overflow IRQ

  • 8 individually enabled, edge-selectable 16-bit (0-65535) edge-transition counters
  • Optional IRQ if 16-bit counter overflows

High- and Low-side Pulse Width Measurement

  • 8 16-bit pulse duration counters for High- and Low-side pulse width measurement
  • 8ns maximum measurement resolution, software divisible by a 32-bit global scalar

PWM Duty Cycle and Frequency Measurement

  • Combine High- and Low-side pulse width measurements to determine waveform duty cycle and frequency

Output Features

Pulse Generation

  • Generate a high- or low-going pulse with selectable active and inactive durations
  • Supports individual or simultaneous pulse generation start
  • 8ns per side max resolution, software divisible by a 32-bit global scalar

Pulse Train Generation

  • Generate up to 65535 consecutive high- or low-going pulses via a per-output 16-bit counter

PWM and Frequency Generation

  • Generate a continuous stream of pulses until stopped.
Note:Not all models will support all of the above features, nor will all models meet the stated specifications. For example, trying to generate a 62.5MHz square wave using an electromechanical relay output is not going to work (what with relay activation times best measured in microseconds) — nor is it possible to generate output pulses if your model has no outputs.

How To Use This Reference

First, read the entirety of this introduction.

Next, read the source code of one of our sample programs and refer to this document for the description of each register used, if needed.

Registers

Overview

PCI and PCI Express (and related) busses are Plug-and-Play, and use a standardized way of requesting resources like register space, IRQs, and DMA channels.

In older designs theses models request two "Base Address Registers" ("BAR"s): BAR[0] is for PEX8311 and PLX9052 compatibility and/or DMA-related registers, and BAR[2] is where all the DAQ-specific (Digital I/O interface) registers and IRQ features resided. Both of these BARs were requested in "I/O space" (aka "Port Memory") accessed via the Intel ASM In and Out instructions. The I/O instructions are inherently slow, designed in the era of the 4.7MHz ISA bus

The new Digital Integration Features versions of these models also requests a 3rd BAR, BAR[1], which contains a copy of the vast majority of the features available in the legacy BAR[2], as well as the new Digital Integration Features' registers, all implemented in "MEM address space" — accessed using pointers these registers can be accessed often as much as 10× faster than the legacy BAR[2] I/O registers.

The new Digital Integration Features consume four 32-bit registers for global control, plus 6 additional registers per-bit to control individual bits' advanced features — all of which are only available in the new, memory-mapped, BAR[1].

Register Map

In addition to the registers defined in each model's product manuals the following registers are available for using the Digital Integration Features (not all models support all registers).

TABLE 1: Global Control Registers added with Digital Integration Features (BAR[1] only)
Offset
Hexadecimal		NameAccess Width1Description
+2CPTG/PTM Clock DivisorDWPulse Train Generation and Measurement features (including PWM I/O) operate in units of "ticks"; this 32-bit value divides the 125MHz base clock (8ns "ticks") down to slower speeds for more flexible pulse measurement and generation
+30CoS IRQ EnablesDW/W/BCopies of the per-bit Bits for enabling IRQ generation on detection of Falling- or Rising-edge input transitions ("Change of State" aka "CoS"), so you can read them simultaneously via a single read
+40IRQ / Event: Status / ClearDW/W/BCopies of the per-bit Bits that indicate if a Rising- or Falling-edge CoS IRQ was generated, and the bits to clear latched IRQ bits, so you can access them simultaneously via a single read or write
+50PTG Start / StatusDW/W/BCopies of the per-bit Pulse Train (PWM) Generation "Go" bits, allowing multiple bits to have PWM or Pulse Trains started simultaneously
+FCResetsBReset bits to return the configuration to the power-on defaults
Note:1 "Access Width" indicates if the register can be read or written using 32-bit ("DW"), 16-bit ("W"), or 8-bit ("B") accessess
TABLE 2: Per-Bit Control Registers added with Digital Integration Features (BAR[1] only)
Per-bit registers are located at "Bit Offsets" starting at (BitIndex+1) × 100 (hexadecimal).
For example, Bit 2's per-bit registers are located at (2 + 1) × 0x100 + Offset = +0x300 + Offset.
Ex: Bit 12's per-bit registers' Bit Offset is (0x0C +1) × 0x100 = +0xD00.
Bit Offset +
Offset
Hexadecimal		NameAccess Width1Description
+00CoS IRQ Enable and Status / ClearDW/W/BCoS Edge Detection IRQ Enable, Status, and Clear bits
+04Event Configuration, Threshold Overflow Status / ClearDW/W/BEvent Edge selection, and Event Counter-Overflow IRQ Enable, Status, and Clear bits
+08Event Counter / PTG CountDW/W/BEvent Detection Counter for Inputs. Pulses-to-generate Counter for Outputs. 16-bit value. Set PWM bit at BitOffset + 10 to generate pulses until stopped
+10PTG Control / StatusDW/W/BPulse Train Generation starting level, finite-or-infinite (PWM) pulses generated, and "GO"/Status bit
+20Pulse LOW PeriodDW/W/B16-bit value. Pulse Width of measured Low-Side pulse for inputs. Low-Side Pulse Width to generate for outputs.
+24Pulse HIGH PeriodDW/W/B16-bit value. Pulse Width of measured High-Side pulse for inputs. High-Side Pulse Width to generate for outputs.
Note:1 "Access Width" indicates if the register can be read or written using 32-bit ("DW"), 16-bit ("W"), or 8-bit ("B") accessess

Register Details

Global Digital Integration Feature Registers

+2C: PTG/PWM Clock Divisor
32-bit value that divides the 125 MHz "Base Clock" to produce the Pulse Train Generation and Measurement feature's "Tick Clock". Each Pulse Counter is only 16-bits wide, so at the full Base Clock the longest high- or low-side pulse width that can be measured is only about 525 µs. Set this 32-bit divisor to increase the 8ns Base Tick rate as desired.
+30: Cos IRQ Enables
Bit31-161514131211109876543210
UseunusedenFE7enFE6enFE5enFE4enFE3enFE2enFE1enFE0enRE7enRE6enRE5enRE4enRE3enRE2enRE1enRE0
enFE[7:0] are IRQ enable bits for Falling-Edge CoS IRQs. enRE[7:0] are enables for Rising-Edge CoS IRQs

Set bits to enable the corresponding IRQ. Clear bits to disable that IRQ. Read to see what CoS IRQs you currently have enabled.

+40: IRQ/Event Status/Clear
Bit31-161514131211109876543210
UseunusedscFE7scFE6scFE5scFE4scFE3scFE2scFE1scFE0scRE7scRE6scRE5scRE4scRE3scRE2scRE1scRE0
scFE[7:0] are IRQ Status and Clear bits for Falling-Edge CoS IRQs. scRE[7:0] are Status and Clear bits for Rising-Edge CoS IRQs.

Read to see what IRQ types have been latched. Write a 1 to latched bits to clear the latch for that bit. Typically you would read this register and write the value read back to the register to clear all detected IRQ latches

+50: PTG Start/Status
Bit31-16151413121110987-0
UseunusedPTG7PTG6PTG5PTG4PTG3PTG2PTG1PTG0unused

Set PTG[7:0] to start the Pulse Generation on the corresponding bit(s). In PWM mode Clear the bit to halt PWM generation. In non-PWM the bit is auto-cleared when the Pulse Train Generation Counter (at + Bit Offset + 10) reaches 0. Read to see which PTG/PWM bits are currently outputting pulse trains/PWMs.

+FC: Resets
Bit31-3210
UseunusedGRSTGRSTCunused
Set GRST to perform a reset of all Digital Integration Feature registers to power-on/reset conditions. Set GRSTC to reset all Event and Pulse Counters. (Bits are auto-cleared by FPGA)

Per-Bit Digital Integration Feature Registers

+0: bit n CoS IRQ Enable and Status/Clear
Bit31-6543210
UseunusedscFE[n]scRE[n]unusedunusedenFE[n]enRE[n]
scFEn is the IRQ Status and Clear bit for Falling-Edge CoS IRQs. scREn is the Status and Clear bit for Rising-Edge CoS IRQs.
enFEn is the IRQ Enable bit for Falling-Edge CoS IRQs. enREn is the IRQ Enable bit for Rising-Edge IRQs
These bits are also available at (Global) +30 and +40 (hexadecimal)

Read scFEn and scREn to see what IRQ types have been latched. Write a 1 to latched bits to clear the latch for that bit. Set enFEn or enREn to enable Falling- or Rising-Edge IRQs for bit n. Read these bits to see if either is enabled. Typically you would read this register and write the value read back to the register to clear the detected IRQ latch(es) while leaving the enabled IRQ sources enabled.

+4: bit n Event Configuration, Threshold Overflow Status / Clear
Bit31-76543210
UseunusedscOverflow[n]unusedenOverflow[n]unusedunusedenFalling[n]enRising[n]
scOverflown is the IRQ Status and Clear bit for Event Counter Overflow IRQs.
enOverflown is the Enable bit for Event Counter Overflow IRQs.
enFallingn enables the Event Counter to count Falling-edge transitions.
enRisingn enables the Event Counter to count Rising-edge transitions.

Read scOverflown to see if an Event Counter Overflow IRQ types has been latched. Write a 1 to clear the latch. Set enFallingn or enRisingn to enable Falling- or Rising-Edge Event Counting for bit n. Read these bits to see if either is enabled. Typically you would read this register and write the value read back to the register to clear the detected IRQ while leaving the Event enable and sources intact.

+8: bit n Event Counter / PTG Count

16-bit Count of enabled and detected Events for input bits, 16-bit number of pulses to generate for output bits (that are not set to PWM mode)

+10: bit n PTG Control / Status
Bit31-3210
UseunusedRising[n]PWM[n]GO[n]

Risingn: Set to cause generated Pulses Trains / PWMs to start with a high-level; clear to start with a low-level. Note: Setting or Clearing this bit causes the output bit to immediately change to the "inactive" state

PWMn: Set to engage PWM mode, wherein the Pulses are generated until stopped, instead of only generating the PTG Count entered at +BitOffset+8

GOn: Set to start PTG/PWM Generation. In PWM mode you can clear GOn to halt the PWM. Read this bit to determine if PTG/PWM Generation is active on bit n

+20: bit n Pulse Low Period

16-bit value. For input bits read to determine the detected low-side pulse width. For outputs write the desired low-side pulse width. In either case the value is measured in number of PTG/PWM ticks. If +2C is configured for ÷1 (the default) this means you multiply the number by 8ns to determine the low-side pulse width in ns. If +2C was configured with a divisor of 125000 then you'd multiply this register value by 1ms to determine the low-side pulse width.

+24: bit n Pulse High Period

16-bit value. For input bits read to determine the detected high-side pulse width. For outputs write the desired high-side pulse width. In either case the value is measured in number of PTG/PWM ticks. If +2C ("PTG/PWM Clock Divisor") is configured for ÷1 (the default) this means you multiply the number by 8ns to determine the high-side pulse width in ns. If +2C was configured with a divisor of 125000 then you'd multiply this register value by 1ms to determine the high-side pulse width.

Example algorithms

Inputs

Pulse Width Measurement

Measure high-side pulse width

  • Configure the PTG/PWM Clock Divisor (at +2C)
  • Ensure the bits are configured for use as inputs (at +3, usually)
  • Read the High-Side pulse width from the register at (BitIndex + 1) × 0x100 + 0x24
  • Multiply the read value by the (8ns × Divisor written to +2C) to get high-side pulse duration in nanoseconds

    • Measure low-side pulse width

  • Configure the PTG/PWM Clock Divisor (at +2C)
  • Ensure the bits are configured for use as inputs (at +3, usually)
  • Read the Low-Side pulse width from the register at (BitIndex + 1) × 0x100 + 0x20
  • Multiply the read value by the (8ns × Divisor written to +2C) to get low-side pulse duration in nanoseconds

    • PWM Duty Cycle Measurement

  • Measure the high-side pulse width
  • Measure the low-side pulse width
  • Divide the high-side pulse width by the sum of the low- and high-Side pulse widths, then multiply by 100 to get Duty Cycle %

    • Edge Counting

    Count number of rising-edges detected with an IRQ to warn of counter overflow

  • Ensure the bits are configured for use as inputs (at +3, usually)
  • Enable the Overflow IRQ and enable rising-edge Event Counting at (BitIndex + 1) × 0x100 + 0x04
  • Have a background thread waiting for IRQs that indicate more than 65535 rising-edge events occurred
  • Read the Event Count register at (BitIndex + 1) × 0x100 + 0x08
  • If one or more Overflow IRQs occurred, add the number of Overflow IRQs × 65536 to get the total number of rising edges detected

    • Outputs

    Generate n high-going Pulses

  • Configure the PTG/PWM Clock Divisor (at +2C)
  • Ensure the bits are configured for use as outputs (at +3, usually)
  • Write the desired number of ticks to the low-side Pulse Width register at (BitIndex + 1) × 0x100 + 0x20
  • Write the desired number of ticks to the high-side Pulse Width register at (BitIndex + 1) × 0x100 + 0x24
  • Write the total number of pulses to generate n to the PTG Count register at (BitIndex + 1) × 0x100 + 0x08
  • Set the Risingn and GOn bits at (BitIndex + 1) × 0x100 + 0x10

    • Generate PWM with 25% Duty Cycle

  • Calculate the total period necessary to generate your base frequency.
  • Configure the PTG/PWM Clock Divisor (at +2C)
  • Ensure the bits are configured for use as outputs (at +3, usually)
  • Write 3/4th the total period in ticks to the low-side Pulse Width register at (BitIndex + 1) × 0x100 + 0x20
  • Write 1/4th the total period in ticks to the high-side Pulse Width register at (BitIndex + 1) × 0x100 + 0x24
  • Set the Risingn, PWMn, and GOn bits at BitIndex + 1) × 0x100 + 0x10

    • Card-specific differences

    Overview

    Not all cards are created equal. As a result some products won't have all these features available. For example, the M.2-II-4 has only four input bits and zero output bits: you cannot generate pulse trains or PWMs, and only 4 out of the 8 input bits are enabled.